Digital to analog conversion circuit and data source circuit chip

ABSTRACT

The present disclosure provides a digital to analog conversion (DAC) circuit and a data source circuit chip, the DAC circuit includes: first MOS tubes with the same number of the inputted digital bits; a second resistance, one end of the second resistance connects to the reference voltage, another end of the second resistance connects to the output terminal of the circuit; a second MOS tube, the drain of the second MOS tube connects to the output terminal of the circuit, the gate of the second MOS tube receives a row blank signal; and a capacitor, one end of the capacitor connects to the output terminal, another end of the capacitor is grounded. Using the above circuit and data source circuit chip, can greatly reduce the number of the MOS tube used in the DAC circuit, to effectively reduce the volume of the data source circuit chip and cost.

BACKGROUND OF THE INVENTION 1. Field of the Disclosure

The present disclosure relates to a signal conversion technology field, and more particularly to a digital to analog conversion circuit reducing the number of the MOS tube and a data source circuit chip for the display panel.

2. Description of the Prior Art

In the working process of the display panel, usually it requires a data source circuit chip (source IC) to convert the digital bit of the control chip (TCON) transmitted to the analog voltage value, then the analog voltage value will charge and discharge the display panel through the display data circuit on the display array, in order to achieve the normal display of the each pixel in the display panel.

In the prior art, typically by the digital to analog conversion module (DAC module) in the Source IC to achieve the conversion from the digital bit to the analog voltage value, and largely the area and cost of the Source IC is decided by the DAC module.

FIG. 1 is a circuit diagram of the DAC module in the Source IC in the prior art, in the present embodiment, with the DAC module inputted three bit (3 bit) as an example, in order to be able to convert the 3 bit to the 8 (8 step) corresponding voltage value, generally require the number of the switching MOS tube is 24 (i.e. 3×2³). If the input of the DAC module is 8 bit, generally require the number of the switching MOS tube is 2048 (i.e. 8×2⁸).

And, each channel in the source IC require the separate DAC module to process the DAC, i.e. if the number of a 8 bit source IC output channel is 960, the number of the required switching MOS tube in the DAC module is up to 1966080 (i.e. 960×2048). If the number of the source IC is 10 bit, the number of the required switching MOS tube is even more.

The number of the MOS tube is greater, result in the volume of the source IC is greater, and the cost is higher.

SUMMARY OF THE DISCLOSURE

The exemplary embodiment of the present disclosure is to provide a digital to analog conversion circuit reducing the number of the MOS tube and a data source circuit chip, effective to reduce the volume of data source circuit chip and reduce costs.

According to an aspect of an exemplary embodiment, there is provided a digital to analog conversion circuit, the circuit includes: first MOS tubes with the same number of the inputted digital bits, wherein, any one of the gate of the first MOS tube receives a digital bit, the any one of the drain of the first MOS tube connects to the output terminal of the circuit, the any one of the source of the first MOS tube connects to the one end of the first resistance, another end of the first resistance connects to a reference voltage, a second resistance, one end of the second resistance connects to the reference voltage, another end of the second resistance connects to the output terminal of the circuit, a second MOS tube, the drain of the second MOS tube connects the output terminal of the circuit, the source of the second MOS tube is grounded, the gate of the second MOS tube receives a row blank signal, a capacitor, one end of the capacitor connects to the output terminal, another end of the capacitor is grounded.

Wherein, the number of the first resistance and the number of the first MOS tube of the circuit included are the same, each value of the first resistance is varied with the varying of the power of the digital bit, wherein the value of the first resistance connected with the highest digital bit and through the first MOS tube is minimum, the value of the first resistance connected with the lowest digital bit and through the first MOS tube is maximum.

Wherein, the value of the second resistance is greater than the value of the first resistance connected with the lowest digital bit.

Wherein, the value of the capacitor is fixed.

Wherein, the any one of the first MOS tube is turned on the any one of the first MOS tube according to the value of the digital bit received from the gate, so that the first resistance of the any one of the first MOS tube connected is accessed into the circuit, between the each first resistance in the accessed circuit is connected in parallel, between the each first resistance and the second resistance in the accessed circuit is connected in parallel.

Wherein, a horizontal scanning period includes a display stage and a display blank stage, the display stage according to the value of the digital bit to charge the capacitor, so that provide the gray voltage of the output terminal of the digital to analog conversion circuit to the display panel, in the display blank stage, all of the first MOS tube are turned off, the second MOS tube is turned on according to the row blank signal, the capacitor is discharged through the second MOS tube, before charging for the capacitor every time, the charge of the capacitor is zero.

Wherein, the value of the each first resistance and second resistance accessed in the circuit after connected in parallel and the gray voltage of the output terminal of the digital to analog conversion circuit are presented as varies nonlinearly.

Wherein, the gray voltage of the output terminal of the digital to analog conversion circuit is calculated by the following equation:

V _(gm) =V _(ref) −V _(ref) ·e ^(−t/RC)

Wherein, V_(gm) is the gray voltage of the output terminal of the digital to analog conversion circuit, V_(ref) is the reference voltage, R is the value of the each first resistance and second resistance in the accessed circuit after connected in parallel, C is capacitor, t is the charge time of the capacitor.

According to another aspect of an exemplary embodiment, there is provided a data source circuit chip, the data source circuit chip includes a receiver, a shift register, a line memory, a level booster circuit and a digital to analog conversion circuit and an amplifying circuit according to claims 1 to 8.

With the above DAC circuit and the data source circuit chip, can greatly reduce the number of the MOS tube required in the DAC circuit, in order to reduce the volume of the data source circuit chip and the cost.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram of the DAC module in the source IC in the prior art;

FIG. 2 is a circuit diagram of the DAC circuit according to the exemplary embodiment shown in the present disclosure;

FIG. 3 is a variation curve of the output voltage of the DAC circuit according to the exemplary embodiment of the present disclosure shown in FIG. 2;

FIG. 4 is a structure diagram with the data source chip of the DAC circuit according to the exemplary embodiment of the present disclosure shown in FIG. 2.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Now it will be hereinafter more fully described with reference to exemplary embodiments of the drawings; however, these examples can be embodied in different forms and embodiments and should not be construed as limited to the embodiments set forth herein. Instead, these embodiments are provided so that this disclosure will be thorough and complete, and the scope of exemplary embodiment will fully convey to those skilled in the art.

The DAC circuit according to the exemplary embodiment of the present disclosure includes a capacitor, a second resistance, a second MOS tube, and first MOS tubes with the same number of the inputted digital bits and first resistances with the same number of the first MOS tube.

Specifically, any one of the gate of the first MOS tube receives a digital bit, the any one of the drain of the first MOS tube connects to the output terminal of the circuit, the any one of the source of the first MOS tube connects to the one end of the first resistance, another end of the first resistance connects to a reference voltage, a second resistance, one end of the second resistance connects to the reference voltage, another end of the second resistance connects to the output terminal of the circuit, a second MOS tube, the drain of the second MOS tube connects the output terminal of the circuit, the source of the second MOS tube is grounded, the gate of the second MOS tube receives a row blank signal, a capacitor, one end of the capacitor connects to the output terminal, another end of the capacitor is grounded.

Refer to FIG. 2, with the DAC circuit inputted 8 bit as an example to describe the working principle of the DAC circuit of the exemplary embodiment of the present disclosure.

FIG. 2 is a circuit diagram of the DAC circuit according to the exemplary embodiment shown in the present disclosure.

Shown in FIG. 2, in the present embodiment, the input of the DAC circuit is 8 bit (i.e. B0˜B7), wherein, B7 is the highest digital bit, B0 is the lowest digital bit, the DAC circuit includes 8 first MOS tubes (i.e. Q0˜Q7) and 8 first resistances (R0˜R7), each connecting method of the first MOS tube are the same, with the first MOS tube Q0 as an example, the gate of the first MOS tube Q0 receives the digital bit B0, the source of the first MOS tube Q0 connects to the one end of the first resistance R0, the other end of the first resistance R0 connects to the reference voltage (Vref), the drain of the first MOS tube Q0 connects to the output terminal of the DAC circuit, here, the first resistance R0 and the first MOS tube Q0 are connected in series as a channel.

Further, the number of the first resistance is the same with the number of the first MOS tube, each value of the first resistance is varied with the varying of the power of the digital bit. Here, as shown in FIG. 2, the value of the first resistance R0˜R7 is gradually reduced, i.e. the value of the first resistance (R7) through the first MOS tube (Q7) connecting with the highest digital bit B7 is lowest, the value of the first resistance (R0) through the first MOS tube (Q0) connecting with the lowest digital bit B0 is biggest.

The one end of the second resistance (R8) connects to the reference voltage (Vref), the other end of the second resistance (R8) connects to the output terminal of the DAC circuit. Here, the value of the second resistance (R8) is greater than the value of the first resistance (R0) connecting with the lowest digital bit B0.

The drain of the second MOS tube (Q8) connects to the output terminal of the circuit, the source of the second MOS tube (Q8) is grounded, the gate of the second MOS tube (Q8) receives the row blank signal (H Blanking), the one end of the capacitor (C3) connects to the output terminal, the other end of the capacitor (C3) is grounded.

The any one of the first MOS tube is turned on the any one of the first MOS tube according to the value of the digital bit received from the gate, so that the first resistance of the any one of the first MOS tube connected is accessed into the circuit, between the each first resistance in the accessed circuit is connected in parallel, between the each first resistance and the second resistance in the accessed circuit is connected in parallel.

Further, the gray voltage of the output terminal of the digital to analog conversion circuit of the exemplary embodiment shown in the present disclosure may calculated by the following equation:

V _(gm) =V _(ref) −V _(ref) ·e ^(−t/RC)  (1)

In the equation (1), V_(gm) is the gray voltage of the output terminal of the digital to analog conversion circuit, V_(ref) is the reference voltage, R is the value of the each first resistance and second resistance in the accessed circuit after connected in parallel, C is capacitor, t is the charge time of the capacitor.

As an exemplary, assuming all the MOS tube (Q0˜Q8) are high conduction, when the digital bit (B0˜B7) are low, all of the first MOS tube (Q0˜Q7) are nonconductive, only the second resistance (R8) is received in the circuit, i.e. the value of the R in the equation (1) is the value of the second resistance R8, in this case, the value of the DAC circuit outputted V_(gm) is the gray voltage value when the corresponding digital bits are all zero (are low).

When the digital bit B0 is high level, the gate of the first MOS tube Q0 received is high level signal, so that the first MOS tube Q0 is turned on, the first resistance R0 connected with the first MOS tube Q0 is accessed in the circuit, in this case, the value of the R in the equation (1) is the value of the first resistance R0 and the second resistance R8 has been connected in parallel, the value of the DAC circuit outputted V_(gm) is the gray voltage value when the corresponding digital bit is 00000001.

Similarly, when the digital bit B0 and B3 is high level, the gate of the first MOS tube Q0 received is high level signal, so that the first MOS tube Q0 is turned on, the first resistance R0 connected with the first MOS tube Q0 is accessed in the circuit, further, the gate of the first MOS tube Q3 receives the high level signal, so that the first MOS tube Q3 is turned on, the first resistance R3 connected with the first MOS tube Q3 is accessed in the circuit, in this case, the value of the R in the equation (1) is the value after the first resistance R0, the first resistance R3, the second resistance R8 connected in parallel, the value of the DAC circuit outputted V_(gm) is the gray voltage value when the corresponding digital bit is 00001001.

Here, according to the above-described manner, after the entire design of the DAC circuit is completed, the value of the capacitor (C3) is fixed, the value of the R in the equation (1) is changed by the change of the number of the first resistance in the access circuit, and then to adjust the output gray voltage value of the DAC circuit.

Further, the value of the each first resistance and second resistance accessed in the circuit after connected in parallel and the gray voltage of the output terminal of the digital to analog conversion circuit are presented as varies nonlinearly.

FIG. 3 is a variation curve of the output voltage of the DAC circuit according to the exemplary embodiment of the present disclosure shown in FIG. 2.

As shown in FIG. 3, the curve performance the relationship between the output voltage of the DAC circuit (i.e. gray voltage V_(gm)) and the R in the equation (1), here, R is the value of the each first resistance and second resistance in the DAC circuit after connected in parallel, further, the trend of the curve shown in FIG. 3 is the same with the trend of the GAMA curve of the display panel, i.e. in line with changes of GAMA curve.

Further, the data source circuit chip (source IC) of the DAC circuit of the exemplary embodiment of the present disclosure is used to provide the gray voltage to the display panel.

FIG. 4 is a structure diagram with the data source chip of the DAC circuit according to the exemplary embodiment of the present disclosure shown in FIG. 2.

As shown in FIG. 4, the data source chip of the exemplary embodiment of the present disclosure includes: a receiver 401, a shift register 402, a line memory 403, a level booster circuit 404, a DAC circuit 405 and an amplifying circuit 406.

Specifically, the receiver 401 converts the differential voltage signal received from the control chip (TCON) to the digital bit signal, and sends the digital bit to the shift register 402 through the serial transmission way.

The shift register 402 converts the serial transmission digital bit signal received from the receiver 401 to be the parallel transmission digital bit signal.

The line memory 403 is arranged the parallel transmission digital bit signal from the shift register 402 by the display position of the display panel, and the digital bit signals are stored according to the order.

The level booster circuit 404 is boosts the working voltage of the digital bit to the analog working voltage.

The DAC circuit 405 is converts the digital bit signal to the analog voltage value (i.e. gray voltage).

Here, as has been described the circuit structure of the DAC circuit 405 in the FIG. 2, the contents of this part of the present disclosure is omitted.

The amplifying circuit 406 amplifies the gray voltage and provides the amplified gray voltage to the display panel.

In the present embodiment, the gray voltage of the data source chip outputted may charge and discharge to the display panel (for example, LCD panel or LED panel) through the display data line on the display array, such that the each pixel in the display panel may accordance with the gray voltage for normal display.

Using the source IC shown in FIG. 4, replacing the DAC circuit of the exemplary embodiment of the present disclosure to the traditional DAC module, the number of the switch MOS tube of the each 8 bit source IC channel required may be reduced from 2048 to 8, greatly reducing the volume of the source IC and the cost.

Refer to FIG. 2, in general, a horizontal scanning period of the display panel includes the display stage and the display blank stage, the each first MOS tube in the DAC circuit in the display stage is turned on by the value of the digital bit, to charge the capacitor, so that provides the corresponding output gray voltage to the display panel, normal displaying the display panel. In this case, the row blank signal is low level signal, the second MOS tube is turned off and not accessed in the circuit.

In the display blank stage, all of the first MOS tube are turned off, in this case, the row blank signal is high level signal, the second MOS tube (Q8) is turned on according to the row blank signal, the capacitor C3 is discharged through the second MOS tube (Q8), the residual charge on the capacitor C3 are all freed, so every time before charging for the capacitor C3, the charge of the capacitor C3 is zero.

As an example, the value of the capacitor (C3) may according to the cross voltage between the highest charge voltage and the lowest charge voltage of the display panel (i.e. the voltage difference between the highest charge voltage and the lowest charge voltage) and the charging time of the display panel to determine the RC value. It should be understood, the R value is the value of the each first resistor and second resistor in the accessed circuit after connected in parallel (i.e. the R value in the equation (1)), the C value is the value of the capacitor C3.

Here, after determining the display panel, the resolution of the display panel will be determined (e.g., 4K or 1080P, or the like), since the charge time of the each line display panel t0 is known, for example, assuming that the resolution of the display panel is 1080P, with 60 frames per second as an example, one frame is corresponded 1080 lines, then the RC should be met within the charging time t0, the charging voltage of the display panel can be boosted a value of one cross voltage.

Using the above DAC circuit and data source circuit chip, can greatly reduce the number of the MOS tube used in the DAC circuit, to effectively reduce the volume of the data source circuit chip and cost. Further, the above DAC circuit and data source circuit chip can also significantly increase the economic efficiency of the source IC products to enhance the competitiveness of the market price of the product.

As already described in conjunction with specific embodiments of the present disclosure, but the embodiment of the present disclosure is not limited thereto. Within the spirit and scope of the present disclosure, those skilled in the art that various modifications and variations, modifications and variations which fall within the scope of protection defined by the claims. 

What is claimed is:
 1. A digital to analog conversion circuit, the circuit comprises: first MOS tubes with the same number of the inputted digital bits, wherein, any one of the gate of the first MOS tube receives a digital bit, the any one of the drain of the first MOS tube connects to the output terminal of the circuit, the any one of the source of the first MOS tube connects to the one end of the first resistance, another end of the first resistance connects to a reference voltage, a second resistance, one end of the second resistance connects to the reference voltage, another end of the second resistance connects to the output terminal of the circuit, a second MOS tube, the drain of the second MOS tube connects to the output terminal of the circuit, the source of the second MOS tube is grounded, the gate of the second MOS tube receives a row blank signal, a capacitor, one end of the capacitor connects to the output terminal, another end of the capacitor is grounded.
 2. The circuit according to claim 1, wherein, the number of the first resistance and the number of the first MOS tube of the circuit comprised are the same, each value of the first resistance is varied with the varying of the power of the digital bit, wherein the value of the first resistance connected with the highest digital bit and through the first MOS tube is minimum, the value of the first resistance connected with the lowest digital bit and through the first MOS tube is maximum.
 3. The circuit according to claim 2, wherein, the value of the second resistance is greater than the value of the first resistance connected with the lowest digital bit.
 4. The circuit according to claim 1, wherein, the value of the capacitor is fixed.
 5. The circuit according to claim 1, wherein, the any one of the first MOS tube is turned on the any one of the first MOS tube according to the value of the digital bit received from the gate, so that the first resistance of the any one of the first MOS tube connected is accessed into the circuit, between the each first resistance in the accessed circuit is connected in parallel, between the each first resistance and the second resistance in the accessed circuit is connected in parallel.
 6. The circuit according to claim 5, wherein, a horizontal scanning period comprises a display stage and a display blank stage, the display stage according to the value of the digital bit charges the capacitor, so that provide the gray voltage of the output terminal of the digital to analog conversion circuit to the display panel, in the display blank stage, all of the first MOS tube are turned off, the second MOS tube is turned on according to the row blank signal, the capacitor is discharged through the second MOS tube, before charging for the capacitor every time, the charge of the capacitor is zero.
 7. The circuit according to claim 5, wherein, the value of the each first resistance and second resistance accessed in the circuit after connected in parallel and the gray voltage of the output terminal of the digital to analog conversion circuit are presented as varies nonlinearly.
 8. The circuit according to claim 7, wherein, the gray voltage of the output terminal of the digital to analog conversion circuit is calculated by the following equation: V _(gm) =V _(ref) −V _(ref) ·e ^(−t/RC) Wherein, V_(gm) is the gray voltage of the output terminal of the digital to analog conversion circuit, V_(ref) is the reference voltage, R is the value of the each first resistance and second resistance in the accessed circuit after connected in parallel, C is capacitor, t is the charge time of the capacitor.
 9. A data source circuit chip, the data source circuit chip comprises a receiver, a shift register, a line memory, a level booster circuit and a digital to analog conversion circuit according to claim 1 and an amplifying circuit.
 10. The data source circuit chip according to claim 9, wherein, the number of the first resistance and the number of the first MOS tube of the circuit comprised are the same, each value of the first resistance is varied with the varying of the power of the digital bit, wherein the value of the first resistance connected with the highest digital bit and through the first MOS tube is minimum, the value of the first resistance connected with the lowest digital bit and through the first MOS tube is maximum.
 11. The data source circuit chip according to claim 10, wherein, the value of the second resistance is greater than the value of the first resistance connected with the lowest digital bit.
 12. The data source circuit chip according to claim 9, wherein, the value of the capacitor is fixed.
 13. The data source circuit chip according to claim 9, wherein, the any one of the first MOS tube is turned on the any one of the first MOS tube according to the value of the digital bit received from the gate, so that the first resistance of the any one of the first MOS tube connected is accessed into the circuit, between the each first resistance in the accessed circuit is connected in parallel, between the each first resistance and the second resistance in the accessed circuit is connected in parallel.
 14. The data source circuit chip according to claim 13, wherein, a horizontal scanning period comprises a display stage and a display blank stage, the display stage according to the value of the digital bit charges the capacitor, so that provide the gray voltage of the output terminal of the digital to analog conversion circuit to the display panel, in the display blank stage, all of the first MOS tube are turned off, the second MOS tube is turned on according to the row blank signal, the capacitor is discharged through the second MOS tube, before charging for the capacitor every time, the charge of the capacitor is zero.
 15. The data source circuit chip according to claim 13, wherein, the value of the each first resistance and second resistance accessed in the circuit after connected in parallel and the gray voltage of the output terminal of the digital to analog conversion circuit are presented as varies nonlinearly.
 16. The data source circuit chip according to claim 15, wherein, the gray voltage of the output terminal of the digital to analog conversion circuit is calculated by the following equation: V _(gm) =V _(ref) −V _(ref) ·e ^(−t/RC) Wherein, V_(gm) is the gray voltage of the output terminal of the digital to analog conversion circuit, V_(ref) is the reference voltage, R is the value of the each first resistance and second resistance in the accessed circuit after connected in parallel, C is capacitor, t is the charge time of the capacitor. 